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cy7c421 256/512/1k/2k/4k 9 asynchronous fifo cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-06001 rev. *f revised december 14, 2010 features asynchronous first-in first-out (fifo) buffer memories ? 512 x 9 (cy7c421) dual-ported ram cell high speed 50 mhz read and write independent of depth and width low operating power: i cc = 35 ma empty and full flags (half full flag in standalone) ttl compatible retransmit in standalone expandable in width plcc, 7x7 tqfp, soj, 300-mil, and 600-mil dip pb-free packages available pin compatible and functionally equivalent to idt7200, idt7201, idt7202, idt7203, idt7204, am7200, am7201, am7202, am7203, and am7204 functional description the cy7c420/1, cy7c424/5, cy7c428/9, and cy7c432/3 are first-in first-out (fifo) memories offered in 600-mil wide and 300-mil wide packages. there are 256, 512, 1,024, 2,048, and 4,096 words respectively by 9 bits wide. each fifo memory is organized such that the data is read in the same sequential order that it was written. full and em pty flags are provided to prevent overrun and underrun. three additional pins are also provided to facilitate unlimited expansion in width, depth, or both. the depth expansion technique steers the control signals from one device to another in parallel. this eliminates the serial addition of propa- gation delays, so that throughput is not reduced. data is steered in a similar manner. the read and write operations may be asynchronous; each can occur at a rate of 50 mhz. the write operation occurs when the write (w ) signal is low. read occurs when read (r ) goes low. the nine data outputs go to the high impedance state when r is high. a half full (hf ) output flag that is va lid in the standalone and width expansion configurations is provided. in the depth expansion configuration, this pin provides the expansion out (xo ) information that is used to tell the next fifo that it is activated. in the standalone and width expansion configurations, a low on the retransmit (rt ) input causes the fifos to retransmit the data. read enable (r ) and write enable (w ) must both be high during retransmit, and then r is used to access the data. the cy7c420, cy7c421, cy7c424, cy7c428, and cy7c432 are fabricated using an advanced 0.65-micron p-well cmos technology. input esd protection is greater than 2000v and latch up is prevented by careful layout and guard rings. table 1. selection guide 4k x 9 ?10 ?15 ?20 ?25 ?30 ?40 ?65 frequency (mhz) 50 40 33.3 28.5 25 20 12.5 maximum access time (ns) 10 15 20 25 30 40 65 i cc1 (ma) 35 35 35 35 35 35 35 cy7c421256/512/1k/2k/4k 9 asynchronous fifo [+] feedback
cy7c421 document #: 38-06001 rev. *f page 2 of 21 logic block diagram ram array 512 x 9 read control write control write pointer reset logic expansion logic data inputs (d 0 ?d 8 ) three- state buffers data outputs (q 0 ?q 8 ) w read pointer flag logic r xi ef ff xo/hf mr fl /rt [+] feedback
cy7c421 document #: 38-06001 rev. *f page 3 of 21 contents features............................................................................. 1 functional description..................................................... 1 logic block diagram........................................................ 2 contents ............................................................................ 3 pin configurations ........................................................... 4 maximum rating............................................................... 5 operating range............................................................... 5 electrical characteristics................................................. 6 capacitance ...................................................................... 6 switching characteristics................................................ 7 switching characteristics................................................ 8 switching waveforms ...................................................... 9 architecture .................................................................... 13 dual-port ram .......................................................... 13 resetting the fifo .................................................... 13 writing data to the fifo ........................................... 13 reading data from the fifo .... ............... .............. .... 13 standalone/width expansion modes ........................ 13 depth expansion mode ............ ............... .............. .... 13 use of the empty and full flags ............................... 14 ordering information...................................................... 15 package diagrams.......................................................... 15 document history page ................................................. 19 sales, solutions, and legal information ...................... 20 worldwide sales and design supp ort............. .......... 20 products .................................................................... 20 psoc solutions ......................................................... 20 [+] feedback
cy7c421 document #: 38-06001 rev. *f page 4 of 21 pin configurations figure 1. 32-pin plcc/lcc (top view) figure 2. 28-p in dip (top view) figure 3. 32-pin tqfp (top view) 4 3 2 1 323130 14 15 1617 181920 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 fl /rt mr ef xo /hf q 7 d 6 q 6 d 7 nc d 2 d 1 d 0 xi ff q 0 q 1 nc q 2 d d w nc v d d 3 8 cc 4 5 q q gnd nc r q q 3 8 4 5 7c421 1 2 3 4 5 6 7 8 9 10 11 12 15 16 17 18 19 20 24 23 22 21 13 14 25 28 27 26 7c420/1 w d 8 d 3 d 2 d 1 d 0 xi ff q 0 q 1 q 2 gnd v cc d 4 fl /rt mr ef xo /hf q 7 r q 3 q 8 d 5 d 6 d 7 q 6 q 5 q 4 7c424 7c428 7c432 26 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 101112131415 32 3130 29 28 27 25 q 1 xi q 0 d 1 d 0 nc nc ff d 6 d 5 d 4 v cc w d 8 d 3 d 2 d 7 fl/rt nc nc mr ef xo/hf q 7 q 2 q 3 q 8 gnd r q 4 q 5 q 6 16 7c421 [+] feedback
cy7c421 document #: 38-06001 rev. *f page 5 of 21 maximum rating exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. [1] storage temperature ................................. ?65 ? c to +150 ? c ambient temperature wit h power applied.. ?55 ? c to +125 ? c supply voltage to ground potentia l................?0.5v to +7.0v dc voltage applied to outputs in high z state ................................................?0.5v to +7.0v dc input voltage ............................................?0.5v to +7.0v power dissipation...................... .................................... 1.0w output current, into outputs (low)............................ 20 ma static discharge voltage....... ........... ............ .............. >2000v (per mil?std?883, method 3015) latch up current ..................................................... >200 ma operating range range ambient temperature [2] v cc commercial 0 ? c to + 70 ? c 5v ? 10% industrial ?40 ? c to +85 ? c 5v ? 10% electrical characteristics over the operating range [3] parameter description test conditions all speed grades unit min max v oh output high voltage v cc = min., i oh = ?2.0 ma 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 v v ih input high voltage commercial 2.0 v cc v industrial 2.2 v cc v il input low voltage [4] 0.8 v i ix input leakage current gnd < v i < v cc ?10 +10 ? a i oz output leakage current r > v ih , gnd < v o < v cc ?10 +10 ? a i os output short circuit current [5] v cc = max., v out = gnd ?90 ma electrical characteristics over the operating range parameter description test conditions ?10 ?15 ?20 ?25 unit min max min max min max min max i cc operating current v cc = max., i out = 0 ma f = f max commercial 85 65 55 50 ma industrial 100 90 80 i cc1 operating current v cc = max., i out = 0 ma f = 20 mhz commercial 35 35 35 35 ma i sb1 standby current all inputs = v ih min. commercial 10 10 10 10 ma industrial 15 15 15 i sb2 power down current all inputs > v cc ?0.2v commercial 5 5 5 5 ma industrial 8 8 8 notes 1. single power supply: the voltage on any input or i/o pin cannot exceed the power pin during power up. 2. t a is the ?instant on? case temperature. 3. see the last page of this specification for group a subgroup testing information. 4. v il (min.) = ?2.0v for pulse durations of less than 20 ns. 5. for test purposes, not more than one output at a time should be shorted. short circuit test duration should not exceed 30 sec onds. [+] feedback
cy7c421 document #: 38-06001 rev. *f page 6 of 21 electrical characteristics over the operating range [3] parameter description test conditions ?30 ?40 ?65 unit min max min max min max i cc operating current v cc = max., i out = 0 ma f = f max commercial 40 35 35 ma industrial 75 70 65 i cc1 operating current v cc = max., i out = 0 ma f = 20 mhz commercial 35 35 35 ma i sb1 standby current all inputs = v ih min. commercial 10 10 10 ma industrial 15 15 15 i sb2 power down current all inputs > v cc ?0.2v commercial 5 5 5 ma industrial 8 8 8 capacitance tested initially and after any design or proces s changes that may affect these parameters. parameter description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 4.5v 6 pf c out output capacitance 6 pf [+] feedback
cy7c421 document #: 38-06001 rev. *f page 7 of 21 switching characteristics over the operating range [6, 7] parameter description ?10 ?15 ?20 ?25 unit min max min max min max min max t rc read cycle time 20 25 30 35 ns t a access time 10 15 20 25 ns t rr read recovery time 10 10 10 10 ns t pr read pulse width 10 15 20 25 ns t lzr [,8] read low to low z 3 3 3 3 ns t dvr [8,9] data valid after read high 5 5 5 5 ns t hzr [,8,9] read high to high z 15 15 15 18 ns t wc write cycle time 20 25 30 35 ns t pw write pulse width 10 15 20 25 ns t hwz [,8] write high to low z 5 5 5 5 ns t wr write recovery time 10 10 10 10 ns t sd data setup time 6 8 12 15 ns t hd data hold time 0 0 0 0 ns t mrsc mr cycle time 20 25 30 35 ns t pmr mr pulse width 10 15 20 25 ns t rmr mr recovery time 10 10 10 10 ns t rpw read high to mr high 10 15 20 25 ns t wpw write high to mr high 10 15 20 25 ns t rtc retransmit cycle time 20 25 30 35 ns t prt retransmit pulse width 10 15 20 25 ns t rtr retransmit recovery time 10 10 10 10 ns t efl mr to ef low 20 25 30 35 ns t hfh mr to hf high 20 25 30 35 ns t ffh mr to ff high 20 25 30 35 ns t ref read low to ef low 10 15 20 25 ns t rff read high to ff high 10 15 20 25 ns t wef write high to ef high 10 15 20 25 ns t wff write low to ff low 10 15 20 25 ns t whf write low to hf low 10 15 20 25 ns t rhf read high to hf high 10 15 20 25 ns t rae effective read from write high 10 15 20 25 ns t rpe effective read pulse width after ef high 10 15 20 25 ns t waf effective write from read high 10 15 20 25 ns t wpf effective write pulse width after ff high 10 15 20 25 ns t xol expansion out low delay from clock 10 15 20 25 ns t xoh expansion out high delay from clock 10 15 20 25 ns notes 6. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v and output loading of the spec ified i ol /i oh and 30 pf load capacitance, as in part (a) of ac test load and waveforms, unless otherwise specified. 7. see the last page of this specification for group a subgroup testing information. 8. t hzr transition is measured at +200 mv from v ol and ?200 mv from v oh . t dvr transition is measured at the 1.5v level. t hwz and t lzr transition is measured at ? 100 mv from the steady state. 9. t hzr and t dvr use capacitance loading as in part (b) of ac test load and waveforms. [+] feedback
cy7c421 document #: 38-06001 rev. *f page 8 of 21 switching characteristics over the operating range [6, 7] (continued) parameter description ?30 ?40 ?65 unit min max min max min max t rc read cycle time 40 50 80 ns t a access time 30 40 65 ns t rr read recovery time 10 10 15 ns t pr read pulse width 30 40 65 ns t lzr [,8] read low to low z 3 3 3 ns t dvr [8,9] data valid after read high 5 5 5 ns t hzr [,8,9] read high to high z 20 20 20 ns t wc write cycle time 40 50 80 ns t pw write pulse width 30 40 65 ns t hwz [,8] write high to low z 5 5 5 ns t wr write recovery time 10 10 15 ns t sd data setup time 18 20 30 ns t hd data hold time 0 0 0 ns t mrsc mr cycle time 40 50 80 ns t pmr mr pulse width 30 40 65 ns t rmr mr recovery time 10 10 15 ns t rpw read high to mr high 30 40 65 ns t wpw write high to mr high 30 40 65 ns t rtc retransmit cycle time 40 50 80 ns t prt retransmit pulse width 30 40 65 ns t rtr retransmit recovery time 10 10 15 ns t efl mr to ef low 40 50 80 ns t hfh mr to hf high 40 50 80 ns t ffh mr to ff high 40 50 80 ns t ref read low to ef low 30 35 60 ns t rff read high to ff high 30 35 60 ns t wef write high to ef high 30 35 60 ns t wff write low to ff low 30 35 60 ns t whf write low to hf low 30 35 60 ns t rhf read high to hf high 30 35 60 ns t rae effective read from write high 30 35 60 ns t rpe effective read pulse width after ef high 30 40 65 ns t waf effective write from read high 30 35 60 ns t wpf effective write pulse width after ff high 30 40 65 ns t xol expansion out low delay from clock 30 40 65 ns t xoh expansion out high delay from clock 30 40 65 ns [+] feedback
cy7c421 document #: 38-06001 rev. *f page 9 of 21 switching waveforms figure 4. asynchronous read and write figure 5. master reset figure 6. half-full flag data valid data valid data valid data valid t sd t hd t rc t pr t a t rr t a t lzr t dvr t hzr t wc t pw t wr r q 0 ?q 8 w d 0 ?d 8 mr r ,w hf ff ef t mrsc t pmr t efl t hfh t ffh t rpw t wpw t rmr [10] [11] half full+1 half full half full w r hf t whf t rhf notes 10. w and r ? v ih around the rising edge of mr 11. t mrsc = t pmr + t rmr . [+] feedback
cy7c421 document #: 38-06001 rev. *f page 10 of 21 figure 7. last write to first read full flag figure 8. last read to first write empty flag figure 9. retransmit [12] switching waveforms (continued) last write first read additional reads first write t wff t rff r w ff valid last read first write additional writes first read valid t ref t wef t a w r ef data out t rtc t prt t rtr fl /rt r ,w [13] notes 12. ef , hf and ff may change state during retransmit as a result of the offset of the read and write pointers, but flags are valid at t rtc . 13. t rtc = t prt + t rtr . [+] feedback
cy7c421 document #: 38-06001 rev. *f page 11 of 21 figure 10. empty flag and read data flow-through mode figure 11. full flag and write data flow-through mode switching waveforms (continued) w r ef data in data out data valid t rae t ref t wef t hwz t a t rpe r w ff data in data out data valid data valid t waf t wpf t wff t rff t sd t hd t a [+] feedback
cy7c421 document #: 38-06001 rev. *f page 12 of 21 figure 12. expansion timing diagrams switching waveforms (continued) r w xo 1 (xi 2 ) d 0 ?d 8 data valid data data valid valid t xol t xoh t hd t sd t sd t hd t xol t lzr t a t dvr t xoh t a t dvr t hzr xo 1 (xi 2 ) q 0 ?q 8 write to last physical location of device 1 write to first physical location of device 2 read from last physical location of device 1 read from first physical location of device 2 t wr t rr data valid [14] [14] note 14. expansion out of device 1 (xo 1 ) is connected to expansion in of device 2 (xi 2 ) [+] feedback
cy7c421 document #: 38-06001 rev. *f page 13 of 21 architecture the cy7c420/1, cy7c424/5, cy7c428/9, cy7c432/3 fifos consist of an array of 256, 512, 1024, 2048, 4096 words of 9 bits each (implemented by an array of dual-port ram cells), a read pointer, a write pointer, control signals (w , r , xi , xo , fl , rt , mr ), and full, half full, and empty flags. dual-port ram the dual-port ram architecture re fers to the basic memory cell used in the ram. the cell itse lf enables the read and write opera- tions to be independent of each other, which is necessary to achieve truly asynchronous operation of the inputs and outputs. a second benefit is that the ti me required to increment the read and write pointers is much less than the time required for data propagation through the memory, which is the case if memory is implemented using the conventiona l register array architecture. resetting the fifo upon power up, the fifo must be reset with a master reset (mr ) cycle. this causes the fifo to enter the empty condition signified by the empty flag (ef ) being low, and both the half full (hf ) and full flags (ff ) being high. read (r ) and write (w ) must be high t rpw /t wpw before and t rmr after the rising edge of mr for a valid reset cycle. if readin g from the fifo after a reset cycle is attempted, the outputs are in the high impedance state. writing data to the fifo the availability of at least one empty location is indicated by a high ff . the falling edge of w initiates a write cycle. data appearing at the inputs (d 0 ?d 8 ) t sd before and t hd after the rising edge of w are stored sequentially in the fifo. the ef low-to-high transition occurs t wef after the first low-to-high transition of w for an empty fifo. hf goes low t whf after the falling edge of w following the fifo actually being half full. therefore, the hf is active after the fifo is filled to half its capacity plus one word. hf remains low while less than one half of total memory is availa ble for writing. the low-to-high transition of hf occurs t rhf after the rising edge of r when the fifo goes from half full +1 to half full. hf is available in standalone and width expansion modes. ff goes low t wff after the falling edge of w , during the cycle in which the last available location is filled. internal logic prevents overrunning a full fifo. writes to a full fifo are ignored and the write pointer is not incremented. ff goes high trff after a read from a full fifo. reading data from the fifo the falling edge of r initiates a read cycle if the ef is not low. data outputs (q 0 to q 8 ) are in a high impedance condition between read operations (r high), when the fifo is empty, or when the fifo is not the active device in the depth expansion mode. when one word is in the fifo, the falling edge of r initiates a high-to-low transition of ef . the rising edge of r causes the data outputs to go to the high impedance state and remain such until a write is performed. re ads to an empty fifo are ignored and do not increment the read poi nter. from the empty condition, the fifo can be read t wef after a valid write. the retransmit feature is beneficial when transferring packets of data. it enables the receiver to acknowledge receipt of data and retransmit, if necessary. the retransmit (rt ) input is active in the standalone and width expansion modes. the retransmit feature is intended for use when a number of writes equal to or less than the depth of the fifo have occurred since the last mr cycle. a low pulse on rt resets the internal read pointer to the first physical location of the fifo. r and w must both be high while and t rtr after retransmit is low. with every read cycle after retransmit, previ- ously accessed data and not previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. full, half full, and empty flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. data wr itten to the fifo after activation of rt are also transmitted. fifo, up to the full depth, can be repeatedly retransmitted. standalone/width expansion modes standalone and width expansion modes are set by grounding expansion in (xi ) and tying first load (fl ) to v cc . fifos can be expanded in width to provide word widths greater than nine in increments of nine. during width expansion mode, all control line inputs are common to all devices, and flag outputs from any device can be monitored. depth expansion mode depth expansion mode (see figure on page 14 ) is entered when, during a mr cycle, expansion out (xo ) of one device is connected to expansion in (xi ) of the next device, with xo of the last device connected to xi of the first device. in the depth expansion mode the first load (fl ) input, when grounded, indicates that this part is the first to be loaded. all other devices must have this pin high. to enable the correct fifo, xo is pulsed low when the last physical location of the previous fifo is written to and pulsed low again when the last physical location is read. only one fifo is enabled for read and one for write at any particular time. all other devices are in standby. fifos can also be expanded simultaneously in depth and width. consequently, any depth or width fifo can be created of word widths in increments of 9. when expanding in depth, a composite ff must be created by oring the ff s together. likewise, a composite ef is created by oring the ef s together. hf and rt functions are not available in depth expansion mode. [+] feedback
cy7c421 document #: 38-06001 rev. *f page 14 of 21 use of the empty and full flags to achieve maximum frequency, the flags must be valid at the beginning of the next cycle. however, because they can be updated by either edge of the re ad or write signal, they must be valid by one-half of a cycl e. cypress fifos meet this requirement; some com petitors? fifos do not. the reason for why the flags sh ould be valid by the next cycle is complex. the ?effective pulse width violation? phenomenon can occur at the full and empty boundary conditions, if the flags are not properly used. the empty fl ag must be used to prevent reading from an empty fifo and the full flag must be used to prevent writing into a full fifo. for example, consider an empty fifo that is receiving read pulses. because the fifo is empty, the read pulses are ignored by the fifo, and nothing happens. next, a single word is written into the fifo, with a signal that is asynchronous to the read signal. the (internal) state machin e in the fifo goes from empty to empty+1. however, it does this asynchronously with respect to the read signal, so that the ef fective pulse width of the read signal cannot be determined, because the state machine does not look at the read signal until it goes to the empty+1 state. similarly, the minimum write pulse width may be violated by trying to write into a full fifo, and asynchronously performing a read. the empty and full flags ar e used to avoid these effective pulse width violations, but to do this and operate at the maximum frequency, the flag must be valid at the beginning of the next cycle. figure 13. depth expansion cy7c420/1 cy7c424 cy7c428 cy7c432 w mr xi fl ef xo ff xi fl ef xo xi fl ef xo ff r empty full q 9 9 9 9 ff v cc * first device * 9 cy7c420/1 cy7c424 cy7c428 cy7c432 cy7c420/1 cy7c424 cy7c428 cy7c432 d [+] feedback
cy7c421 document #: 38-06001 rev. *f page 15 of 21 ordering information speed (ns) ordering code package diagram package type operating range 15 cy7c421?15axc 51-85063 32-pin thin plastic quad flatpack (pb-free) commercial 20 cy7c421?20jxc 51-85002 32-pin plastic leaded chip carriers (pb-free) commercial cy7c421?20vxc 51-85031 28-pin (300-mil) molded soj (pb-free) cy7c421?20jxi 51-85002 32-pin plastic leaded chip carrier (pb-free) industrial ordering code definitions temperature range: x = c or i c = commercial; i = industrial x = pb-free (rohs compliant) package type: xx = a or j or v a = 32-pin tqfp j = 32-pin plcc v = 28-pin molded soj speed: 15 ns or 20 ns 1 = depth: 512 2 = width: 9 4 = fifo technology code: c = cmos 7 = dual port sram cy = cypress device c cy 4 - xx xx 7 2 x 1 x [+] feedback
cy7c421 document #: 38-06001 rev. *f page 16 of 21 package diagrams figure 14. 32-pin thin plastic quad flat pack, 51-85063 51-85063 *c [+] feedback
cy7c421 document #: 38-06001 rev. *f page 17 of 21 figure 15. 32-pin plastic leaded chip carrier, 51-85002 51-85002 *c [+] feedback
cy7c421 document #: 38-06001 rev. *f page 18 of 21 figure 16. 28-pin (300-mil) pdip, 51-85014 51-85014 *e [+] feedback
cy7c421 document #: 38-06001 rev. *f page 19 of 21 figure 17. 28-pin (300-mil) molded soj, 51-85031 51-85031 *d [+] feedback
cy7c421 document #: 38-06001 rev. *f page 20 of 21 document history page document title: cy7c421 256/51 2/1k/2k/4kx9 asynchronous fifo document number: 38-06001 rev. ecn no. orig. of change submission date description of change ** 106462 szv 07/11/01 change from spec number: 38-00079 to 38-06001 *a 122332 rbi 12/30/02 added power up requirements to maximum ratings information. *b 383597 pcx see ecn added pb-free logo added to part-ordering information: cy7c419?10jxc, cy7c419?15jxc, cy7c419-15vxc, cy7c421?10jxc, cy7c421?15axc, cy7c421?20jxc, cy7c421?20vxc, cy7c425?10axc, cy7c425?10jxc, cy7c425?15jxc, cy7c425?20jxc, cy7c425?20vxc, cy7c429?10axc, cy7c429?15jxc, cy7c429?20jxc, cy7c433?10axc, cy7c433?10jxc, cy7c433?15jxc, cy7c433?20axc, cy7c433?20jxc *c 2623658 vkn/pyrs 12/17/08 added cy7c421-20jxi removed cy7c419/25/29/33 from the ordering information table removed 26-lead cerdip, 32-lead rlcc, 28-lead molded dip packages from the data sheet removed military information *d 2714768 vkn/aesa 06/04/2009 corrected defective logic block diagram, pinouts, and package diagrams *e 2896039 rame 03/19/2010 added contents. removed inactive parts from the data sheet. updated all package diagrams. updated links in sales, solutions, and legal information *f 3110157 admu 12/14/2010 added ordering code definitions . [+] feedback
document #: 38-06001 rev. *f revised december 14, 2010 page 21 of 21 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c421 ? cypress semiconductor corporation, 2005-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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